Bit-detection arrangement and apparatus for reproducing information

ABSTRACT

Described is an invention relating to a bit-detection arrangement able to convert an analog signal (AS) into a digital signal (DS). The analog signal (AS) is fed to a quantizer ( 11 ). After the quantizer ( 11 ) the output signal S 1  is fed to a phase detector PD 1  ( 12 ). Also samples are taken of the output signal S 1 . The output signal PH 2  (of the phase detector PD 1  ( 12 ) is dependent on the phase difference between the output signal S 1  and the clock signal C 2 . If the frequency of the clock signal C 2  is approximately equal to the frequency of the output signal S 1  then the output signal PH 2  of the phase detector PD 1  ( 12 ) varies slowly. The analog to digital converter ADC ( 13 ) can therefore sample the output at a slow rate, dictated by the clock signal C 1 . The clock signal C 1  is derived from C 2  by dividing clock signal C 2  by a factor n, whereby n is greater than one. To obtain the phase differences at clock periods of clock signal C 2 , the processed signal PrS of the analog to digital converter ADC ( 13 ) is interpolated. This can be done in different ways. A special embodiment comprises a digital phase locked loop DPLL ( 2 ) with discrete time oscillators. The obtained phase differences are used by the bit decision unit ( 3 ) to output the samples.

The invention relates to a bit-detection arrangement able to convert an analog signal having an amplitude into a digital signal representing a bit sequence from which the analog signal is derived, comprising:

a preprocessing unit able to convert the analog signal into a processed signal suitable for further processing and able to produce an output signal S₁, comprising an analog to digital converter ADC which is able to output the processed signal at a sample rate controlled by a clock signal C₁;

a digital phase locked loop DPLL able to lock on the processed signal and able to output a phase signal PH₁ using the clock signal C₁, and

a bit decision unit able to output the digital signal and a clock signal C₃ using the phase signal PH₁, the clock signal C₁ and the output signal S₁.

The invention also relates to an apparatus for reproducing information on an information carrier having such a bit-detection arrangement.

An embodiment of such a bit-detection arrangement is known from European Patent Application 0342736.

The known bit-detection arrangement converts the analog signal into the processed signal by using the analog to digital converter ADC of the preprocessing unit. The processed signal thus comprises samples of the analog signal. The analog to digital converter ADC is controlled by the clock signal C₁, which has a frequency of approximately the bit rate or greater of the bit sequence from which the analog signal is derived. The bits in the bit sequence will hereinafter also be referred to as channel bits. The bit rate of the channel bits in the analog signal will hereinafter also be referred to as the channel bit rate, or the channel bit frequency. The digital PLL is able to output the phase signal PH₁ which indicates the channel bit rate. The bit decision unit is able to determine a first crossing with a predetermined level of the phase signal PH₁, and is able to output the digital signal by determining a sign of a sample of the analog signal at an instant in time in the neighborhood of the first crossing by using the processed signal. Therefore, in this case, the processed signal is used as signal S₁ mentioned in the opening paragraph. The bit decision unit is able to output the clock signal C₃ which is synchronous with the digital data. Clock signal C₃ is derived from the phase signal PH₁. Clock signal C₃ is used to clock out the correct bits at the correct moments. The known bit-detection arrangement also comprises an interpolator which determines the phase difference between a zero crossing of the clock signal C₁ and a zero crossing of the processed signal. According to this phase difference the phase of the processed signal is corrected and subsequently fed to the digital PLL.

It is apparent that the analog to digital converter ADC has to sample at a rate determined by the channel bit rate. With increasing demands on the channel bit rate, the analog to digital converter ADC also has to sample at increasing rates. It is a drawback of the known bit-detection arrangement that it is not able to process analog signals with relatively high channel bit rates. Furthermore, an analog to digital converter ADC that can sample with relatively high sample rates is relatively expensive. Also the speed at which the digital PLL operates is determined by the channel bit rate, and therefore the demands on the digital PLL become higher with increasing channel bit rates.

It is a first object of the invention to provide a bit-detection arrangement of the kind described in the opening paragraph, that is able to process analog signals with relatively high channel bit rates, and even also at relatively low costs.

It is a second object of the invention to provide an apparatus for reproducing information recorded on an information carrier, which is provided with such a bit-detection arrangement.

The first object is realized in that the bit-detection arrangement further comprises a clock divider able to use a clock signal C₂ to produce the clock signal C₁ by dividing a frequency of the clock signal C₂ by a factor n, where n is an integer greater than one, and the preprocessing unit further comprises:

a quantizer able to produce the output signal S₁ by quantizing the amplitude of the analog signal, and

a phase detector PD₁ able to determine a phase difference ΔP₁ between the output signal S₁ and the clock signal C₂, and able to feed an output signal PH₂ having an amplitude, where the amplitude of PH₂ indicates the phase difference ΔP₁, to the analog to digital converter ADC, and

the bit decision unit comprising a sample and hold unit able to sample the output signal S₁, using the clock signal C₂, and to hold n samples, sample_(y=1) to sample_(y=n), of the output signal S₁ for a clock period of clock signal C₁, n being the division factor of clock signal C₂.

The output signal PH₂ of the phase detector PD₁ has a relatively low frequency if the difference of the frequency of the clock signal C₂ and the output signal S₁ is relatively small. Therefore the analog to digital converter ADC can sample at a relatively slow rate, and thus the ADC may be a relatively simple and inexpensive one. For this reason the clock signal C₁ may have a lower frequency than clock signal C₂, in fact clock signal C₁ is derived from clock signal C₂ by dividing the frequency of clock signal C₂ by a factor n. The analog to digital converter ADC is able to use the clock signal C₁ to control the sample rate, resulting in the processed signal.

The quantizer quantizes the analog signal. A common used quantizer is a threshold detector. The threshold detector converts the analog signal into a digital signal. If the analog signal is above a predetermined threshold level, then the output signal S₁ has a value 1. Otherwise the output signal has a value 0. The sample and hold unit now can sample these 0's and 1's. Also the phase detector PD, can be implemented digitally, so that it can be simpler and work at higher frequencies.

The bit decision unit is able to use the phase signal PH, to produce the digital signal which is synchronous in relation to the channel bits, thereby being able to use the clock signal C₁ to output the digital signal. The sample and hold unit is capable of holding n samples. This unit is read out every cycle of clock signal C₁, and during each cycle of clock signal C₁ there are n cycles of clock signal C₂. The n samples comprise a number of channel bits which number is dependent on the ratio of the channel bit frequency and the frequency of clock signal C₂. For instance, if the frequency of clock signal C₂ is approximately equal to the channel bit frequency, then the n samples comprise n channel bits. If the frequency of clock signal C₂ is one and a half times the channel bit frequency, then the n samples comprise 2n/3 channel bits. If, with this ratio, n equals 3, then 3 samples contain 2 channel bits.

So, one sample may contain a duplicate value of a channel bit which is already represented by an other sample. If the phase difference exceeds a predetermined value, then the corresponding sample is the sample that may contain a duplicate value and the bit decision unit may decide not to output that sample in the digital signal. The decision not to output a sample will hereinafter also be referred to as discarding a sample. Because the amplitude of the processed signal represents the phase difference, it can be determined from the processed signal which sample to discard. Because the digital phase locked loop locks to the processed signal, also signal PH₁ may be used for determining which sample to use and which sample to discard. Initial, the phase difference and thus the amplitude of PH₁ may start from zero. When the amplitude exceeds a predetermined value then a corresponding sample may be discarded. The corresponding sample may be the sample closest to the point in time where the predetermined value is crossed. After that crossing, every time a multiple of the predetermined value is crossed, a corresponding sample may be discarded.

If the frequency of clock signal C₂ is approximately equal to the channel bit frequency, then the frequency of the processed signal is relatively low. Then also PH₁ has a relatively low frequency. Because the amplitude of PH₁ is only known at sampling instants determined by clock signal C₁, the amplitudes of PH₁ corresponding to the samples of S₁ have to be determined, e.g. by interpolating the amplitude at the n sampling instants. This results in the amplitude of PH₁ at n points between each cycle of clock signal C₁. If the amplitude of PH₁ at one of the n points exceeds a multiple of the predetermined value, then the corresponding sample of S₁ may be discarded.

If the frequency of PH₁ is relatively low, then the moments at which the amplitude of PH₁ exceeds a multiple of the predetermined value are relatively rare. This results in almost every sample of S₁ being outputted into the digital signal. This is the desired result, because when the frequency of PH₁ is relatively low, the frequency of the clock signal C₂ and the channel bit rate is approximately the same. If those frequencies are exactly the same, then all samples are outputted.

If the frequency of PH₁ is relatively high, then the moments at which the amplitude of PH₁ exceeds a multiple of the predetermined value are relatively frequent. This results in a smaller number of samples of S₁ being outputted into the digital signal between two subsequent cycles of clock signal C₁.

If n equals one, then the analog to digital converter ADC samples at the same speed as the analog to digital converter ADC of the known bit detection arrangement. Thus when n equals one the objective of the invention is not achieved. The clock signal that is fed to the digital phase locked loop DPLL and the bit decision unit does not explicitly has to be clock signal C₁. A clock signal that fulfills the Nyquist criterion for the processed signal will suffice. Because clock signal C₂ always has a higher rate than clock signal C₁, clock signal C₂ may be used instead of clock signal C₁ in case of the digital phase locked loop DPLL and the bit decision unit.

In an embodiment n is equal to eight. Because many digital systems work with units of eight bits this embodiment is relatively easy implementable. However n can have other values, provided that n is an integer. If n equals one, then the bit-detection arrangement does not fulfill the object of the invention, because the ADC has to sample at a relatively high rate. Common values of n are powers of 2, e.g. 16, 64, 128 or 256.

It follows from the previous paragraphs that for deriving the digital signal from the analog signal, the analog to digital converter ADC does not have to sample at a rate equal to or greater than the channel bit rate. A lower rate than the channel bit rate suffices because the phase signal PH₂ has a relatively low frequency. In the known bit-detection arrangement on the contrary, the analog to digital converter ADC has to sample at a relatively high rate, in order to satisfy the Nyquist criterion.

In an embodiment of the arrangement according to the invention the phase signal PH₁ comprises n components indicating which of the n samples is valid at a moment indicated by the clock signal C₁, n having the aforementioned value. The digital phase locked loop DPLL may generate the n components in a same manner as described in previous paragraphs, i.e. by interpolating the phase signal PH₁ and determine whether the amplitude of PH₁ has exceeded a multiple of the predetermined value.

In a favorable embodiment the amplitude of the output signal PH₂ is inversely proportional to the phase difference ΔP₁, and the phase locked loop DPLL comprises:

a phase detector PD₂ able to generate a phase difference signal ΔP₂ which is indicative for a phase difference between the processed signal and a feedback signal;

an integrating low pass filter able to produce a filtered signal by filtering the phase difference signal ΔP₂;

n discrete time oscillators DTO_(x=1) to DTO_(x=n), each DTO comprising:

-   -   a multiplicator able to produce a multiplied signal which is a         multiplication of the filtered signal (Fs) with a factor x equal         to the index x of the DTO, and     -   a summator able to produce a summated signal SUM_(x) which is a         summation of the multiplied signal and the feedback signal;     -   a truncation unit able to produce a truncated signal by         resetting all bits in a bit presentation of the summated signal         SUM_(n) which are more significant than k least significant bits         in the bit presentation, and able to produce the n components of         the phase signal PH₁ wherein a first component has a value 1 if         bit k+1 in a bit presentation of a sample of the summated signal         SUM₁ has a value other than bit k+1 in a bit presentation of an         immediately preceding sample of the summated signal SUM_(n),         indicating that sample_(y=1) is valid, and wherein an xth         component, where x is greater than 1, of the phase signal has a         value 1 if bit k+1 in a bit presentation of the summated signal         SUM_(x) has a value other than bit k+1 in a bit presentation of         the summated signal SUM_(x−1), indicating that sample_(y=x) is         valid, and     -   a buffer able to produce the feedback signal by holding the         value of the truncated signal for one clock period of the clock         signal C₁.

The DPLL is able to synchronize the feedback signal with the processed signal. If the clock signal C₂ has a frequency approximately the same as the channel bit frequency, then all the samples may be outputted in the digital signal, i.e. all samples are valid. This means that bit k+1 in the bit presentation of the summated signal SUM_(n) differs from bit k+1 in the bit presentation of the summated signal SUM_(n) of one clock period of clock signal C₁ ago, and that bit k+1 in the bit presentation of the summated signal SUM_(x), where x is greater than 1, differs from bit k+1 in the bit presentation of the summated signal SUM_(x−1) of all the summated signals. In this situation the filtered signal has a value approximately equal to the value represented by bit k+1 in the bit presentations of the summated signals, so that bit k+1 alternates between the bit presentations of the subsequent summated signals.

If the channel bit frequency decreases, then the frequency of the processed signal increases. At the sampling moment of clock signal C₁ the amplitude of the processed signal decreases because the signal is inversely proportional to the phase difference ΔP₁. Consequently the amplitude of the feedback signal decreases too. This is accomplished by lowering the value of the filtered signal. Because the filtered signal is lowered, at some time bit k+1 of the bit presentation of a summated signal SUM_(x) is has the same value as bit k+1 of the summated signal SUM_(x−1). This bit is not valid and is not outputted in the digital signal.

If the digital PLL is in lock, then the phase difference signal ΔP₂ has a near zero value. Because of the integrating effect in the integrating low pass filter the filtered signal preserves its value, thereby preserving the frequency of the feedback signal.

The interpolation described before is in this embodiment in fact performed by the n discrete time oscillators DTO_(x=1) to DTO_(x=n).

In an example n is equal to eight, and at one sampling instant bits k+1 of the signals SUM₁ to SUM₈ are:

SUM₁=0, SUM₂=1, SUM₃=0, SUM₄=0,

SUM₅=1, SUM₆=0, SUM₇=1, SUM₈=0.

In this case bit k+1 has the same values when comparing SUM₃ and SUM₄. This implies that the sample_(y=4) may be discarded.

If the phase difference signal ΔP₂ changes slowly then the feedback signal changes quickly and bit k+1 of the summated signals SUM_(x) more frequently toggles. This is a logical outcome, because if the phase difference signal ΔP₂ has a low frequency, then the frequency of the clock signal C₂ is approximately equal to the channel bit frequency, and thus almost every sample may be outputted. If the phase difference signal ΔP₂ changes more quickly then the feedback signal changes more slowly and bit k+1 of the summated signals SUM_(x) less frequently toggles. In this case the frequency of the clock signal C₂ is higher than the channel bit frequency, and some samples may be discarded. The samples in the sample and hold unit can be clocked out parallel using the clock signal C₁. In that case clock signal C₂ is used as clock signal C₃. The digital signal DS then comprises the n samples in the sample and hold unit. The digital signal DS also comprises the n components of phase signal PH₁ to indicate which of the n samples are valid. Alternatively, the n samples of the sample and hold unit may be clocked out serial using clock signal C₃, where clock signal C₃ is obtained by serializing the n components of phase signal PH₁ within the clock period of clock signal C₁.

A further embodiment further comprises:

a voltage controlled oscillator able to produce the clock signal C₂ having a frequency dependent on a VCO voltage, and

a frequency detector able to produce the VCO voltage dependent on a frequency of a signal chosen from output signal S₁, output signal PH₂ and the processed signal, the frequency detector being designed to handle the chosen signal.

Because in this embodiment the frequency of the clock signal C₂ is related to the frequency of output signal S₁, output signal PH₂ or the processed signal, and thus also to the channel bit frequency, the number of bits in the digital signal is held constant. If the frequency of the clock signal C₂ is approximately equal to the channel bit frequency, all the samples can be outputted in the digital signal every clock cycle of clock signal C₁. If output signal S₁ is used, then the frequency measured is directly the channel bit rate and the frequency of the VCO can be established accordingly. Also, the frequency detector and the VCO can operate in the analog domain. When using output signal PH₂ then the measured frequency is a measure of the frequency difference between the clock signal C₂ and the channel bit rate. The VCO is controlled to minimize this difference. Here, also the frequency detector and the VCO can operate in the analog domain. If the processed signal is used, then again the measured frequency is the frequency difference between the clock signal C₂ and the channel bit rate. The processed signal is however a digital signal, so the frequency detector in this case is designed to handle digital signals.

In a still further embodiment the bit-detection arrangement further comprises location determining means able to output a location signal which is indicative for relative positions of locations where the output signal S₁ crosses a predetermined level L₁ and where the clock signal C₂ crosses a predetermined level L₂, and the bit decision unit is able to use the location signal to determine if a sample may be toggled.

Because the phase of clock signal C₂ is not locked to the phase of the output signal S₁, the sample and hold unit may take samples which have an other value than the corresponding channel bit. This situation could occur around so called zero crossings. A zero crossing is the point where the amplitude of an AC-signal has a zero value. If the signal also has an DC component, then the zero crossing is defined as the point where the amplitude of the signal has a value of that DC-component. In this embodiment the zero crossings are determined by comparing the signals with the predetermined levels L₁ and L₂.

The phase difference between clock signal C₂ and output signal S₁ can be so great that the sample and hold unit samples at an area around zero crossing. In the following example presume that clock signal C₂ lags the output signal S₁, meaning that the sampling moments are later in time than the timing of the channel bits. If the clock signal C₂ indicates to the sample and hold unit to sample before the zero crossing of the output signal S₁, then the sample has a correct value in relation to the corresponding channel bit. If, however, the clock signal C₂ indicates that the sample and hold unit samples after the zero crossing of the output signal C₂, then the sample has an other value than the corresponding channel bit. This sample may be toggled in order for it to have a correct value.

When a bit may be toggled, the location signal has a value indicating this. The bit decision unit then may toggle the corresponding sample.

In an embodiment of the bit-detection arrangement the preprocessing unit comprises first conversion means for:

generating a first converted signal which is derived from the output signal PH₂ by removing steep transitions by switching between an inverting and an non-inverting state when the phase difference ΔP₁ exhibits a steep phase change;

feeding the converted signal to the analog to digital converter ADC, and

outputting a control signal that indicates the phase changes,

and in that the digital phase locked loop DPLL further comprises second conversion means which is able to generate a second converted signal which is derived from the processed signal P_(r)S by adding steep transition by switching between an inverting and an non-inverting state by using the control signal.

In previous embodiments the output signal PH₂ exhibits a steep transition when the phase difference ΔP₁ goes from 359 degrees to 0 degrees. This transition sets high demands on the performance of the analog to digital converter ADC. The first conversion means take away the steep transitions. Therefore the demands on the analog to digital converter ADC can be relaxed. The second conversion means puts back the transitions so that further processing by the digital phase locked loop DPLL can be the same as in previous embodiments.

The second object of the invention is realized in that the apparatus for reproducing information recorded on an information carrier is provided with the bit-detection arrangement according to the invention.

Such an apparatus generally also comprises:

a read head able to read information from the information carrier;

a displacement means able to cause a relative displacement between the information carrier and the read head;

a signal processing unit able to process a signal coming from the read head into the analog signal;

a channel decoding means able to decode the digital signal.

The apparatus for reproducing information on an information carrier is able to use a bit-detection arrangement having an analog to digital converter with a relative slow sampling rate.

These and other aspects of the bit-detection arrangement and of the apparatus for reproducing information according to the invention will be apparent from and elucidated by means of the drawings, in which:

FIG. 1 shows an embodiment of the bit-detection arrangement according to the invention;

FIG. 2 a shows an example of the analog signal;

FIG. 2 b shows a signal that represents the channel bit rate in the example of FIG. 2 a;

FIG. 2 c shows the clock signal C₂ in the example of FIG. 2 a;

FIG. 2 d shows the output signal PH₂ in the example of FIG. 2 a;

FIG. 3 shows an example of the processed signal in relation to the clock signals C₁ and C₂;

FIG. 4 shows an embodiment of a DPLL which is able to output a phase signal PH₂ which comprises 8 components indicating which of the 8 samples is valid;

FIG. 5 a shows an example of the feedback signal in relation to the processed signal;

FIG. 5 b shows another example of the feedback signal in relation to the processed signal;

FIG. 6 shows possible embodiments of the bit-detection arrangement comprising a frequency detector and a voltage controlled oscillator;

FIG. 7 shows an embodiment of the bit-detection arrangement comprising a location determining means;

FIG. 8 a shows an example of the output signal S₁ in relation to the sample moments of clock signal C₂, where a sample is taken before zero crossing;

FIG. 8 b shows an example of the output signal S₁ in relation to the sample moments of clock signal C₂, where a sample is taken after zero crossing;

FIG. 9 shows an embodiment of the bit detection arrangement using inverting means;

FIG. 10 a shows an example of the phase difference ΔP₁;

FIG. 10 b shows the output signal PH₂ when using the first inverting means in case of the phase difference ΔP₁ shown in FIG. 10 a;

FIG. 10 c shows an example of the control signal in case of the phase difference ΔP₁ shown in FIG. 10 a, and

FIG. 11 shows an embodiment of an apparatus for reproducing information provided with a bit-detection arrangement of the invention.

In the embodiment of the bit-detection arrangement shown in FIG. 1 the analog signal AS is converted into the processed signal PrS by the preprocessing unit 1. The digital phase locked loop DPLL 2 locks on to the processed signal PrS and outputs a phase signal PH₁. The bit decision unit outputs the digital signal DS and the clock signal C3 using the phase signal PH₁, the clock signal C₁ and the output signal S₁. The clock divider 4 produces the clock signal C₁ by dividing the frequency of clock signal C₂ by a factor n. The quantizer 11 quantizes the amplitude of the analog signal AS and outputs the resulting signal S₁. The phase detector PD₁ 12 determines the phase difference ΔP₁ between the output signal S₁ and the clock signal C₂ and feeds the output signal PH₂ to the ADC. The ADC then samples the output signal PH₂ at a rate controlled by the clock signal C₁. The sample and hold unit 31 samples the output signal S₁ to obtain binary samples using the clock signal C₂. At the end of a clock cycle of clock signal C₁ the sample and hold unit 31 contains n samples. The bit decision unit may output all these samples at the beginning of the next cycle of clock signal C₁, or it outputs a smaller selection of these samples. Some samples may be discarded.

In FIG. 2 a the analog signal AS 5 is shown together with a level 8. In the next example an embodiment of the quantizer 11 is a threshold detector. A threshold detector interprets samples as a logic 1 if the value of the sample is above a predetermined level, and as a logic 0 if the value of the sample is under a predetermined level. The level 8 shown in FIG. 2 a is the predetermined level. The sampling moments of clock signal C₂ are indicated by the circles 6. The sampling moments of the original data is indicated by the crosses 7. In FIG. 2 b the rising edges of the pulses indicate the sampling moments corresponding to the crosses 7, i.e. this signal represents the channel bit rate. The rising edges of the pulses in FIG. 2 c indicate the sampling moments corresponding to the circles 6, i.e. this signal represents the clock signal C₂.

The channel bits contained in the analog signal AS of FIG. 2 a are 1111 0001. The data that the sample and hold unit contains after sampling the output signal S₁ is 1111 1 0001. It is clear that one channel bit is sampled twice. In this case the fifth bit, i.e. sample_(y=5), that the sample and hold unit 31 contains, may be discarded.

Further in FIG. 2 d it is apparent that the output signal PH₂, indicated by the solid line, has a relatively low frequency compared to the channel bit rate. The ADC 13 may sample at a relatively low rate. The output signal PH₂ is noisy because of disturbance in the clock signal C₂ and because the phase difference ΔP₁ does not exactly have a linear course. Therefore also the processed signal P_(r)S is noisy because it is a sampled version of the output signal PH₂. The digital PLL 2 smoothens the processed signal P_(r)S in order to oppress these disturbances.

As can be seen from the FIGS. 2 a to 2 d, at a first point the phase difference between the clock signal C₂ and the channel bit rate becomes so great that one channel bit is sampled twice. This first point corresponds to a second point at which the amplitude of the output signal PH₂ crosses a predetermined value. Because ADC 13 samples at a clock cycle which is n times slower than the clock cycle of clock signal C₂, it is not clear from the processed signal PrS which of the n samples that the sample and hold unit 31 contains may be discarded. As shown in FIG. 3 however, the processed signal PrS may be interpolated to obtain information about which sample may be discarded. The first sample corresponding to the interpolation that is greater than the predetermined level L, may be discarded. A next sample may be discarded that has a corresponding interpolation that is greater than twice the predetermined value L. If the processed signal PrS at some point returns to zero, than of course the criterion for discarding the next sample is crossing the predetermined level L. In FIG. 3 C ₁ and C₂ are the cycles of the corresponding clock signals. If the embodiment of the digital PLL 2 outputs a similar signal as the processed signal PrS, then instead of the processed signal P_(r)S also the phase signal PH₁ may be used. In that case the interpolation may be done by the bit detection unit 3.

In FIG. 4 the phase detector 21 outputs a phase difference signal ΔP₂ which is filtered by the integrating low pass filter 22. The filtered signal FS is fed to the multiplicators 231 to 238. The multiplied signals are fed to the summators 241 to 248. The summated signals SUM₁ to SUM₈ are then fed to the truncator 25. The summated signal SUM₈ is truncated by the truncator and then fed as the truncated signal T_(r)S to the buffer 26. Truncating in this context means resetting all bits in a bit presentation of the summated signal SUM₈ which are more significant than k least significant bits in the bit presentation. If the summated signal SUM₈ of DTO_(—)8 has a value of decimal 83, then a bit presentation of that sample of 8 bits is 0101 0011. If k equals 4 than the truncated signal T_(r)S sample equals 0000 0011, which represents decimal 3. The truncated signal T_(r)S is clocked into the buffer by clock signal C₁, and outputted as the feedback signal FB for one clock cycle of C₁. The feedback signal FB is added to the multiplied signals by the summators 241 to 248. Also the phase of the feedback signal FB is compared to the phase of the processed signal P_(r)S by the phase detector 21. The phase signal PH, contains 8 components S₁V to S₈V. The signals S₁V to S₈V indicate which of the 8 samples is valid at a moment indicated by the clock signal C₁. Hereinafter a value 1 of these signals indicate that the corresponding sample is valid and may be outputted in the digital signal DS.

In FIG. 5 a an example of the processed signal P_(r)S, the feedback signal FB and a signal representing the channel bit frequency ChBf are shown, whereby n equals 8. On the horizontal axis periods of clock signal C₁ and clock signal C₂ are inserted. The feedback signal FB and the processed signal P_(r)S are clocked with clock signal C₁. Clock signal C₂ is included for illustration purposes. In this example the clock signal C₂ has a slightly higher frequency than the channel bit frequency ChBf. As a result, the processed signal P_(r)S is varying relatively slowly. At every clock period of clock signal C₁ the feedback signal FB is buffered. The phase detector PD₂ 21 tries to synchronize the feedback signal FB with the processed signal P_(r)S If that is the case, then the momentary amplitude of the feedback signal FB is substantially equal to the amplitude of the processed signal P_(r)S. Because almost all samples obtained by the sample and hold unit 31 may be outputted in the digital signal DS, bits k+1 of subsequent summated signals SUM_(x) are alternating. This means that the filtered signal FS has a relatively high value. If for example bit k+1 represents a decimal value of 256, then the filtered signal FS has a value of approximately 250. This causes bit k+1 of subsequent summated signals SUM_(x) to alternate, and the signals S₁V to S₈V have a value 1, indicating all the samples may be outputted.

In FIG. 5 b the channel bit frequency ChBf is substantially lower than the channel bit frequency ChBf of the example shown in FIG. 5 a. This causes the processed signal P_(r)S to vary more quickly. As a consequence the frequency of the feedback signal FB decreases in order to synchronize the feedback signal FB with the processed signal P_(r)S. The filtered signal FS is decreased in order to decrease the frequency of the feedback signal FB. The filtered signal FS may, for instance, have a value of 200. At one point bit k+1 of subsequent summated signals SUM_(x) does not alternate, and the corresponding sample is not outputted.

In the embodiment depicted in FIG. 6 the clock signal C₂ is produced by the voltage controlled oscillator VCO. The frequency detector produces the VCO voltage as a function of the frequency of the output signal PH₂, or the frequency of the processed signal PrS, or the frequency of the output signal S₁. The voltage controlled oscillator VCO and the Frequency detector FD of an embodiment using the frequency of the output signal PH₂ or the output signal S₁ can be implemented with analog electronics. The frequency detector FD of an embodiment using the processed signal P_(r)S, is preferably implemented digitally, because the processed signal PrS is digital. Also the relation between the VCO voltage and the frequency of the input signal of the frequency detector FD is dependent on the signal used as the input signal of the frequency detector FD. For instance, the output signal S₁ has a higher frequency than the processed signal PrS.

The location determining means LDM in FIG. 7 is able to determine the location of the zero crossing of the output signal S₁ and the location of the zero crossing of the clock signal C₂. If, as indicated in FIG. 8 a, the sample 6 is taken just before the zero crossing of the output signal S₁, then the value of the sample is 1. The corresponding channel bit 7 also has a value 1, so the sample has the correct value. If, as indicated in FIG. 8 b, the sample 6 is taken just after the zero crossing of the output signal, then the value of the sample is 0. The value of the sample is thus incorrect and may be toggled. The location signal may indicate to the bit decision unit to toggle this sample. The location signal can for instance be a bit-stream with the same frequency as clock signal C₂, but with value 0 if the corresponding bit is preferably not to be toggled and a value 1 if the corresponding bit is preferably to be toggled.

In FIG. 9 the output signal PH₂ is fed to an input of the first conversion means 14. The first inverted signal CvS₁ is fed to the analog to digital converter ADC 13. Also a control signal CS is generated by the first conversion means 14. The control signal CS is fed to the second conversion means 27. The second conversion means 27 uses the control signal CS to put back the steep transitions.

In FIG. 10 a the output signal PH₂ exhibits several steep transitions. Between point P1 and point P2, as shown in FIG. 10 b, the output signal PH₂ is inverted, thereby removing the two steep transitions at the points P1 and P2. Also a control signal CS is generated as can be seen in FIG. 10 c. In this example the control signal CS contains pulses at the steep transitions. The second conversion means 27 operate in a similar manner.

In FIG. 11 the displacement means 200 displaces the information carrier 100 relative to the read head 300. The signal processing unit 400 converts a signal coming from the read head 300 into the analog signal AS. The read head 300 could for instance be a laser unit and a detector for detecting a laser beam reflected by the surface of the information carrier 100. The detector can contain four sub-detection areas. The signal processing unit 400 then performs a summation operation to the signals coming from the sub-detection areas. The analog signal AS is subsequently converted to the digital signal DS by the bit detection arrangement 500 of the invention. Following that conversion, the channel decoding means 600 further decodes the digital signal DS. The digital signal DS can for instance be a EFM coded signal. 

1. Bit-detection arrangement able to convert an analog signal (AS) having an amplitude into a digital signal (DS) representing a bit sequence from which the analog signal (AS) is derived, comprising: a preprocessing unit (1) able to convert the analog signal (AS) into a processed signal (PrS) suitable for further processing and able to produce an output signal S₁, comprising an analog to digital converter ADC (13) which is able to output the processed signal (PrS) at a sample rate controlled by a clock signal C₁; a digital phase locked loop DPLL (2) able to lock on the processed signal (PrS) and able to output a phase signal PH₁ using the clock signal C₁ and a bit decision unit (3) able to output the digital signal (DS) and a clock signal C₃ using the phase signal PH₁, the clock signal C₁ and the output signal S₁, characterized by the presence of a clock divider (4) able to use a clock signal C₂ to produce the clock signal C₁ by dividing a frequency of the clock signal C₂ by a factor n, where n is an integer greater than one, and the preprocessing unit (1) further comprising: a quantizer (11) able to produce the output signal S₁ by quantizing the amplitude of the analog signal (AS), and a phase detector PD₁ (12) able to determine a phase difference AP, between the output signal S₁ and the clock signal C₂, and able to feed an output signal PH₂ having an amplitude, where the amplitude of PH₂ indicates the phase difference ΔP₁, to the analog to digital converter ADC (13), and the bit decision unit (3) comprising a sample and hold unit (31) able to sample the output signal S₁, using the clock signal C₂, and to hold n samples, sample_(y=1) to sample_(y=1), of the output signal S₁ for a clock period of clock signal C₁, n being the division factor of clock signal C₂.
 2. Bit-detection arrangement as claimed in claim 1, characterized in that the phase signal PH₁ comprises n components indicating which of the n samples is valid at a moment indicated by the clock signal C₁.
 3. Bit-detection arrangement as claimed in claim 2, characterized in that the amplitude of the output signal PH₂ is inversely proportional to the phase difference ΔP₁, and in that the phase locked loop DPLL (2) comprises: a phase detector PD₂ (21) able to generate a phase difference signal ΔP₂ which is indicative for a phase difference between the processed signal (PrS) and a feedback signal (FB); an integrating low pass filter (22) able to produce a filtered signal (Fs) by filtering the phase difference signal ΔP₂; n discrete time oscillators DTO_(x=1) to DTO_(x=n), each DTO comprising: a multiplicator able to produce a multiplied signal which is a multiplication of the filtered signal (Fs) with a factor x equal to the index x of the DTO, and a summator able to produce a summated signal SUM_(x) which is a summation of the multiplied signal and the feedback signal (FB); a truncation unit (25) able to produce a truncated signal (TrS) by resetting all bits in a bit presentation of the summated signal SUM_(n) which are more significant than k least significant bits in the bit presentation, and able to produce the n components of the phase signal PH₁ wherein a first component has a value 1 if bit k+1 in a bit presentation of a sample of the summated signal SUM₁ has a value other than bit k+1 in a bit presentation of an immediately preceding sample of the summated signal SUM_(n), indicating that sample_(y=1) is valid, and wherein an xth component, where x is greater than 1, of the phase signal has a value 1 if bit k+1 in a bit presentation of the summated signal SUM_(x) has a value other than bit k+1 in a bit presentation of the summated signal SUM_(x−1), indicating that sample_(y=x) is valid, and a buffer (26) able to produce the feedback signal (FB) by holding the value of the truncated signal (TrS) for one clock period of the clock signal C₁.
 4. Bit-detection arrangement as claimed in claim 1, characterized in further comprising: a voltage controlled oscillator (VCO) able to produce the clock signal C₂ having a frequency dependent on a VCO voltage, and a frequency detector (FD) able to produce the VCO voltage dependent on a frequency of a signal chosen from output signal S₁, output signal PH₂ and the processed signal (PrS), the frequency detector (FD) being designed to handle the chosen signal.
 5. Bit-detection arrangement as claimed in claim 1, characterized in further comprising location determining means (LDM) able to output a location signal which is indicative for relative positions of locations where the output signal S₁ crosses a predetermined level L₁ and where the clock signal C₂ crosses a predetermined level L₂, and the bit decision unit (3) is able to use the location signal to determine if a sample may be toggled.
 6. Bit-detection arrangement as claimed in claim 1, characterized in that n is equal to eight.
 7. Bit-detection arrangement as claimed in claim 1, characterized in that the preprocessing unit (1) comprises first conversion means (14) for: generating a first converted signal (CvS₁) which is derived from the output signal PH₂ by removing steep transitions by switching between an inverting and an non-inverting state when the phase difference ΔP₁ exhibits a steep phase change; feeding the converted signal (CvS₁) to the analog to digital converter ADC (13), and outputting a control signal (CS) that indicates the phase changes, and in that the digital phase locked loop DPLL (2) further comprises second conversion means (27) which is able to generate a second converted signal (CVS₂) which is derived from the processed signal P_(r)S by adding steep transition by switching between an inverting and an non-inverting state by using the control signal (CS).
 8. Apparatus for reproducing information recorded on an information carrier (100), provided with the bit-detection arrangement as claimed in claim
 1. 